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The multiple phase implementation results in better system performance, superior thermal management, lower component cost, reduced power dissipation, and smaller implementation area. Compared with the traditional multiphase buck regulator, the R3 modulator commands variable switching frequency during load transients, which achieves faster transient response. With the same modulator, the switching frequency is reduced at light load conditions resulting higher operation efficiency.

The ISLC has several other key features. ISLC reports output power through a power monitor pin. Current datahseet can be achieved by using either inductor DCR or discrete precision resistor.

A unity gain, differential amplifier is available for remote voltage sensing. Precision Multiphase Core Voltage Regulation – 0. Superior Noise Immunity and Transient Response?

Power Monitor and Thermal Monitor? Differential Remote Voltage Sensing? Programmable 1, 2 or 3 Power Channels? Excellent Dynamic Current Balance between Channels?

ISL datasheet & applicatoin notes – Datasheet Archive

These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. All Rights Reserved All other trademarks mentioned are the property of their respective owners. A current source is connected internally to this pin. VW pin sources current. FB This pin is the inverting input of error amplifier. VSEN Remote core voltage sense input. Connect to microprocessor die. RTN Remote voltage sensing return. Connect to ground at microprocessor die. When asserted low, indicates a reduced load-current condition.

DFB Inverting input to droop amplifier. VO An input to the IC that reports the local output voltage. PMON An analog output. VSUM This pin is connected to the current summation junction.

VIN Battery supply voltage, used for feed forward. VSS Signal ground; Connect to iisl6260 controller ground. Datxsheet 5V bias power. ISEN3 Individual current sensing for channel 3. It affects both soft start and VID transitioning slew rate. Soft pin is the non-inverting input of the error amplifier. ISEN2 Individual current sensing for channel 2. ISEN1 Individual current sensing for channel 1. It will disable diode emulation. A high level logic signal on this pin enables the regulator.

At steady state, a high level logic signal on this pin indicates that the micro-processor is in Deeper Sleep Mode. Between active and sleep mode transition, high logic level on this pin programs slow C4 entry and exit; low logic level on this pin programs large charging or discharging soft pin current, and therefore fast output voltage transition slew rate.

A low level logic signal on this pin indicates that the micro-processor is in Deeper Sleep Mode. Do not operate at or near the maximum datqsheet listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. See Tech Brief TB for details. Electrical Specifications Operating Conditions: Temperature limits established by characterization and are not production tested.


Limits established by characterization and are not production tested. A capacitor is added in parallel with RL in order to improve the stability margin of the channel current balance loop. No NTC thermistor is needed and the droop circuit is simplified. It can be programmed for one- two- or three-channel operation for microprocessor core applications up to 70A. The ISLC modulator internally synthesizes analog signals inside the IC emulating the inductor ripple currents and use hysteretic comparators on those signals to determine switching pulse widths.

Operating on these large-amplitude, noise-free synthesized signals allows the ISLC to achieve lower output ripple and lower phase jitter than conventional hysteretic and fixed PWM mode catasheet. Unlike conventional hysteretic converters, the ISLC has an error amplifier that allows the controller to maintain a 0.

At heavy load conditions, the ISL is switching at a relatively constant switching frequency similar to fixed frequency PWM controller. At light load conditions, the ISLC is switching at a frequency proportional to load current similar to hysteretic mode controller.

And the power monitor pin provides an analog signal representing the output power of the converter.

(PDF) ISL6260 Datasheet download

During this interval, isl6620 SOFT capacitor is charged with approximately 40? A typical start-up timing is shown in Figure The ISLC provides for current osl6260 be sensed using resistors in series with the channel inductors as shown in the application circuit of Figure 40 or using the intrinsic series resistance of the inductors as shown in the application circuit of Figure When using ratasheet DCR current sensing, a single NTC element is used to compensate the positive temperature coefficient of the copper winding thus sustaining the load-line accuracy with reduced cost.

The IBAL circuit will adjust the channel pulse-widths up or down relative to the other channels to cause the voltages presented to the ISEN pins to be equal.

However, the switching frequency variation will be kept small to maintain the output voltage ripple within SPEC. In general, the switching frequency will be very close to the set value at high input voltage and heavy load conditions.

ISL6260 Datasheet PDF

As load is further reduced, channel switching frequency will drop, providing optimized efficiency at light loading. Only if the inductor current is really cross zero, does the true DCM occur. Intersil’s R3 intrinsically has voltage-feed-forward. The output voltage is insensitive to a fast slew input voltage change. The hysteresis window voltage is constructed with a resistor on the Vw pin to the error amplifier outputs.

The synthesized inductor current ripple signal compares with the window voltage and generates PWM signal. At load current step up, the switching frequency is increased resulting in a faster response than conventional fixed frequency PWM controllers. As all the phases shares the same hysteretic window voltage, it also ensures excellent dynamic current balance between phases. The individual average phase voltages are monitored and controlled to achieve steady state current balance among the phases with current balance loop.


The overcurrent and way-overcurrent protection level in two-to-one phase mode operation will be adjusted as two-to-one as well. Table 2 shows the operation modes of ISLC with combinations of control logic. When PSI is de-asserted low, ISEN2 pin is connected to the ISEN pins of the operational phases internally to keep proper current balance and minimize the inductor current overshoot and undershoot when the disabled phase is enabled again.

This protection was referred to as way-overcurrent or fast over current, for short-circuit protections. In addition, excessive phase unbalance due to gate driver failure will be detected and will shut down the controller. The phase unbalance is detected by the voltage on the ISEN pin. Undervoltage protection is independent of the overcurrent limit. If the output voltage is less than the VID set value by mV or more, a fault will latch after 1ms in that condition. This is shown in Figure Note that most practical core voltage regulators will have the overcurrent set to trip before the mV undervoltage limit.

There are two levels of overvoltage protection with different response. All of the above faults have the same action taken: When these inputs are returned to their high operating levels, a soft-start will occur.

The second level of overvoltage protection behaves differently. If the output exceeds 1. The low-side FETs will remain on until the output voltage is pulled down below 0. If the output again rises above 1. This affords the maximum amount of protection against a shorted high-side FET while preventing output ringing below ground.

Overcurrent protection is related to dxtasheet voltage droop which is determined by the load line requirement. After the load-line is set, the OCSET resistor can be selected to detect overcurrent at any level of droop voltage. For overcurrent less that 2. If the voltage on the NTC pin goes below the 1. Fault protection is summarized in Table 3.

The two slew rates are determined by the currents into the SOFT pin. Also, the SOFT pin is the input to the error amplifier and is, therefore, the commanded datasbeet voltage.

Depending on the state of the system, i. Start-Up or Active mode, and the state of the DPRSLPVR pin, one of the two currents shown in Figure 44 will be used to charge or discharge this capacitor, thereby controlling the slew rate of the commanded voltage. Power Monitor The power monitor signal is an analog output.